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| LD3986 SERIES DUAL ULTRA LOW DROP-LOW NOISE BICMOS VOLTAGE REG. FOR USE WITH VERY LOW ESR OUT. CAPACITORS s s s s s s s s s s s s INPUT VOLTAGE FROM 2.5V TO 6V STABLE WITH LOW ESR CERAMIC CAPACITORS ULTRA LOW DROPOUT VOLTAGE (60mV TYP. AT 150mA LOAD, 0.4mV TYP. AT 1mA LOAD) VERY LOW QUIESCENT CURRENT (155A TYP. AT NO LOAD, 290A TYP. AT 150mA LOAD; MAX 2A IN OFF MODE) GUARANTEED OUTPUT CURRENT UP TO 150mA FOR BOTH OUTPUTS DUAL OUTPUT VOLTAGES FAST TURN-ON TIME: TYP. 120s (CO=1F, CBYP=10nF AND IO=1mA) LOGIC-CONTROLLED ELECTRONIC SHUTDOWN INTERNAL CURRENT AND THERMAL LIMIT OUTPUT LOW NOISE VOLTAGE 30VRMS OVER 10Hz to 100KHz S.V.R. OF 50dB AT 1KHz, 40dB AT 10KHz TEMPERATURE RANGE: -40C TO 125C Flip-Chip DESCRIPTION The LD3986 provides up to 150mA at each output, from 2.5V to 6V input voltage. The ultra low drop-voltage, low quiescent current and low noise make it suitable for low power applications and in battery powered systems. Regulator ground current increases only slightly in dropout, further prolonging the battery life. Power supply rejection is 50 dB at 1KHz and 40 dB at 10KHz. High power supply rejection is maintained down to low input voltage levels common to battery operated circuits. Shutdown Logic Control function is available for each output, this means that when the device is used as local regulator, it is possible to put a part of the board in standby, decreasing the total power consumption. The LD3986 is designed to work with low ESR ceramic capacitors. Typical applications are in mobile phone and similar battery powered wireless systems. Figure 1: Schematic Diagram September 2005 Rev. 3 1/12 LD3986 SERIES Table 1: Order Codes Flip-Chip LD3986J12248R Flip-Chip (Lead Free) LD3986J122R-E LD3986J12248R-E LD3986J1828R-E LD3986J2528R-E (*) LD3986J28R-E LD3986J285R-E LD3986J29R-E (*) LD3986J30R-E (*) LD3986J2830R-E (*) LD3986J3133R-E (*) LD3986J33R-E 1 OUTPUT VOLTAGES 1.22 V 1.22 V 1.8 V 2.5 V 2.8 V 2.85 V 2.9 V 3.0 V 2.8 V 3.1 V 3.3 V 2 OUTPUT VOLTAGES 1.22 V 4.8 V 2.8 V 2.8 V 2.8 V 2.85 V 2.9 V 3.0 V 3.0 V 3.3 V 3.3 V LD3986J285R (*) Available on Request. Table 2: Absolute Maximum Ratings Symbol VI VO1,2 VEN1,2 IO PD TSTG TOP DC Input Voltage DC Output Voltage ENABLE Input Voltage Output Current Power Dissipation Storage Temperature Range Operating Junction Temperature Range Parameter Value -0.3 to 6 -0.3 to VI+0.3 -0.3 to VI+0.3 Internally limited Internally limited -65 to 150 -40 to 125 C C Unit V V V Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Table 3: Thermal Data Symbol Rthj-amb Parameter Thermal Resistance Junction-Ambient Flip-Chip 120 Unit C/W 2/12 LD3986 SERIES Figure 2: Pin Connection (top through view) Table 4: Pin Description Symbol VO2 EN2 BYPASS GND GND EN1 VO1 VI Pin N A1 B1 C1 C2 C3 B3 A3 A2 Output Voltage 2 of the dual LDO Enables voltage for output voltage 2: ON MODE when VEN 1.4V, OFF MODE when VEN 0.4V (Do not leave floating, not internally pulled down/up) Bypass Pin: Connect an external capacitor (usually 10nF) to minimize noise voltage Common Ground Common Ground Enables voltage for output voltage 1: ON MODE when VEN 1.4V, OFF MODE when VEN 0.4V (Do not leave floating, not internally pulled down/up) Output Voltage 1 of the dual LDO Input Voltage for both LDO Name and Function Figure 3: Typical Application Circuit 3/12 LD3986 SERIES Table 5: Electrical Characteristics For LD3986 (Tj = 25C, VI = VO(NOM) +0.5V, CI = C O =1F, CBYP = 10nF, IO = 1mA, VEN = 1.4V, unless otherwise specified) Symbol VI VO VO VO VO IQ Parameter Operating Input Voltage Output Voltage Tolerance Line Regulation (Note 1) Load Regulation IO = 1mA TJ= -40 to 125C VI = VO(NOM) + 0.5 V to 6V TJ= -40 to 125C IO = 1 mA to 150mA TJ= -40 to 125C Output AC Line Regulation VI = VO(NOM) + 1 V, IO = 150mA, (See fig. 5) tR= tF = 30s Quiescent Current BOTH ON MODE: VEN = 1.4V IO = 0 IO = 0 IO = 0 to 150mA IO = 0 to 150mA BOTH OFF MODE: VEN = 0.4V ONE REGULATOR ON MODE: VEN = 1.4V TJ= -40 to 125C IO = 0 IO = 0 IO = 0 to 150mA IO = 0 to 150mA VDROP Dropout Voltage (Note 2) IO = 1mA IO = 1mA IO = 150mA IO = 150mA SVR Supply Voltage Rejection (See fig. 4) Short Circuit Current Peak Output Current Enable Input Logic Low (Note 3) Enable Input Logic High (Note 3) Enable Input Current Crosstalk Rejection TJ= -40 to 125C 50 40 600 300 TJ= -40 to 125C 1.4 VEN = 0.4V VI = 6V 10 40 40 30 50 160 VRMS s C nA V 550 0.4 VI = VO(NOM)+0.25V f = 1KHz VRIPPLE = 0.1V, IO= 50mA f = 10KHz VO(NOM) < 2.5V, VI = 2.55V RL = 0 VO VO(NOM) - 5% VI = 2.5V to 6V TJ= -40 to 125C 50 100 dB TJ= -40 to 125C 0.4 2 TJ= -40 to 125C 165 220 mV 95 130 TJ= -40 to 125C 0.001 TJ= -40 to 125C 290 370 2 4 1.5 150 200 0.003 Test Conditions Min. 2.5 -2.5 -3 0.006 Typ. Max. 6 2.5 3 0.092 0.128 0.006 0.01 mVPP A %/mA %/V Unit V % of VO ISC IO(PK) VEN mA mA V IEN XTALK ILOAD1 = 150 mA at 1KHz rate ILOAD2 = 1 mA, VO2 under test ILOAD2 = 150 mA at 1KHz rate ILOAD1 = 1 mA, VO1 under test eN tON TSHDN Output Noise Voltage Turn On Time (Note 4) Thermal Shutdown (Note 4) BW = 10 Hz to 100 KHz CBYP = 10 nF (Note 3) CO = 1 F 4/12 LD3986 SERIES Symbol CO Parameter Output Capacitor Capacitance ESR Test Conditions Min. 1 0.005 Typ. Max. 22 5 Unit F Note 1: For VO< 2V, VI=2.5V Note 2: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply for input voltages below 2.5V. Note 3: Enable pin must be driven with a TR = TF < 10ms Note 4: Turn-on time is time measured between the enable input just exceeding VINH High Value and the output voltage just reaching 95% of its nominal value Note 5: Typical thermal protection hysteresis is 20C Figure 4: SVR Input Voltage Test Signal Figure 5: AC Line Regulation Input Voltage Test Signal 5/12 LD3986 SERIES TYPICAL PERFORMANCE CHARACTERISTICS (Tj = 25C, VI = VO(NOM) +0.5V, CI = CO = 1F, CBYP = 10nF, IO = 1mA, VEN = 1.4V, unless otherwise specified) Figure 6: VO1,2 vs Temperature Figure 9: Load Regulation vs Temperature Figure 7: VO1,2 vs Temperature Figure 10: Quiescent Current vs Temperature Figure 8: Line Regulation vs Temperature Figure 11: Quiescent Current vs Temperature 6/12 LD3986 SERIES Figure 12: Supply Voltage Rejection vs Frequency Figure 15: Load Transient Response IO1 = 1 mA, IO2 = 0mA, TR = TF = 10s Figure 13: Supply Voltage Rejection vs Temperature Figure 16: TURN-ON VI = 3.2V, VEN1,2 = 0 to 1.4V, IO1,2 = 1mA, TR = TF = 1s Figure 14: Line Transient Response Figure 17: TURN-OFF VI = 3.2V to 3.8V, IO1 = IO2 = 150mA, TR = TF = 10s VI = 3.2V, VEN1,2 = 1.4 to 0V, IO1,2 = 1mA, TR = TF = 1s 7/12 LD3986 SERIES APPLICATION INFORMATION CURRENT LIMIT The device includes short-circuit protection. It includes a current limiter that controls the pass transistor's gate voltage to limit the output current to about 600mA. THERMAL OVERLOAD PROTECTION The Thermal over load protection limits total power dissipation in the device. When the junction temperature (TJ) exceeds +160C, the thermal sensor sends a signal to the shutdown logic, turning off the pass transistors and allowing the device to cool. The pass transistors turns on again after the device's junction temperature typically cools by 20C, resulting in a pulsed output during continuous thermal overload conditions. POWER DISSIPATION Maximum power dissipation of the device depends on the thermal resistance of the case and circuit board, the temperature difference between the die junction and ambient air, and the rate of air flow. The power dissipated by the device is: PD = IO (VI -VO) The maximum power dissipation is: PMAX = (TJMAX - TA) / RTH Where: TJMAX = +125C TA is the ambient temperature RTH thermal resistance. The device's pins perform the dual function of providing an electrical connection as well as channeling heat away from the die. Use wide circuit-board traces and large, solid copper polygons to improve power dissipation. Using multiple vias to buried ground planes further enhances thermal conductivity. INPUT CAPACITOR An input capacitance of 1F is required between the LD3986 input pin and ground (the amount of the capacitance may be increased without limit). This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. 8/12 Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will be 1F over the entire operating temperature range. OUTPUT CAPACITOR The LD3986 is designed specifically to work with very small ceramic output capacitors, any ceramic capacitor (temperature characteristics X7R, X5R, Z5U or Y5V) in 1 to 22 F range with 5m. to 500m. ESR range is suitable in the LD3986 application circuit. it may also be possible to use tantalum or film capacitors at the output, but these are not as attractive for reasons of size and cost. The output capacitor must meet the requirement for minimum amount of capacitance and also have an ESR (Equivalent Series Resistance) value which is within a stable range. NOISE BYPASS CAPACITOR Connecting a 0.01F capacitor between the CBYP pin and ground significantly reduces noise on both regulator outputs. This cap is connected directly to a high impedance node in the band gap reference circuit. Any significant loading on this node will cause a change on the regulated output voltage. For this reason, DC leakage current through this pin must be kept as low as possible for best output voltage accuracy. The use of this 0.01F bypass capacitor is strongly recommended to prevent overshoot on the output during start up. The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High-quality ceramic capacitors with either NPO or COG dielectric typically have very low leakage. Polypropylene and polycarbonate film capacitors are available in small surface-mount packages and typically have extremely low leakage current. Unlike many other LDO's, addition of a noise reduction capacitor does not effect the transient response of the device. TURN-ON/OFF INPUT OPERATION Each LD3986 output is turned off by pulling the relevant EN pin low, and turned on by pulling it high. To assure proper operation, the signal LD3986 SERIES source used to drive the EN input must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under Enable Input Logic Low and Enable Input Logic High. Proper operation of the Enable function is guaranteed by driving EN pins with TR and TF = 10 ms. FAST ON-TIME The LD3986 outputs are turned on after VREF voltage reaches its final value (1.23V nominal). To speed up this process, the noise reduction capacitor at the bypass pin is charged with an internal 70A current source. The current source is turned off when the bandgap voltage reaches approximately 95% of its final value. The turn on time is determined by the time constant of the bypass capacitor. The smaller the capacitor value, the shorter the turn on time, but less noise gets reduced. As a result, turn on time and noise reduction need to be taken into design consideration when choosing the value of the bypass capacitor. 9/12 LD3986 SERIES Flip-Chip8 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b D D1 E E1 e f ccc 0.45 1.52 0.265 1.52 0.585 0.21 TYP 0.65 0.25 0.40 0.315 1.57 1 1.57 1 0.5 0.285 0.080 0.55 17.7 1.62 59.8 0.365 1.62 10.4 59.8 MAX. 0.715 0.29 MIN. 23.0 8.3 TYP. 25.6 9.8 15.7 12.4 61.8 39.4 61.8 39.4 19.7 11.2 3.1 20.7 63.8 14.4 63.8 MAX. 28.1 11.4 mils 7224720E 10/12 LD3986 SERIES Table 6: Revision History Date 07-Dec-2004 06-Jun-2005 22-Sep-2005 Revision 1 2 3 Description of Changes First Release. Add New Part Number - Table 1. Order Codes has been updated. 11/12 LD3986 SERIES Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 12/12 |
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